View NBSG86AMNHTBG_9022278.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2014 june, 2014 ? rev. 19 1 publication order number: nbsg86a/d nbsg86a 2.5v/3.3v?sige differential smart gate with output level select the nbsg86a is a multi?function differential logic gate which can be configured as an and/nand, or/nor, xor/xnor, or 2:1 mux. this device is part of the gigacomm ? family of high performance silicon germanium products. the device is housed in a 3 x 3 mm 16 pin qfn package. differential inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), lvcmos/lvttl, cml, or lvds. the output level select (ols) input is used to program the peak?to?peak output amplitude between 0 and 800 mv in five discrete steps. the nbsg86a employs input default circuitry so that under open input conditions (d x , d x , vtd x , vtd x, vtsel) the outputs of the device will remain stable. features ? maximum input clock frequency > 8 ghz typical ? maximum input data rate > 8 gb/s typical ? 165 ps typical propagation delay ? 40 ps typical rise and fall times ? selectable swing pecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? selectable swing necl output with necl inputs with operating range: v cc = 0 v with v ee = ?2.375 v to ?3.465 v ? selectable output level (0 v, 200 mv, 400 mv, 600 mv, or 800 mv peak?to?peak output) ? 50 internal input termination resistors ? this is a pb?free device marking diagram* http://onsemi.com a = assembly location l = wafer lot y = year w = work week = pb?free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. qfn16 mn suffix case 485g 1 see detailed ordering and shipping information on page 16 o f this data sheet. ordering information 16 sg 86a alyw 1 ??
nbsg86a http://onsemi.com 2 vtd1 d1 d1 vtd1 vtd0 d0 d0 vtd0 v ee q q v cc ols sel sel vtsel 5678 16 15 14 13 12 11 10 9 1 2 3 4 nbsg86a exposed pad (ep) figure 1. qfn16 pinout (top view) table 1. pin description pin name i/o description 1 ols (note 3) input input pin for the output level select (ols). see table 2. 2 sel ecl, cml, lvcmos, lvds, lvttl input inverted differential select logic input. 3 sel ecl, cml, lvcmos, lvds, lvttl input noninverted differential select logic input. 4 vtsel ? common internal 50 termination pin for sel/sel . see table 7. (note 1) 5 vtd1 ? internal 50 termination pin. see table 7. (note 1) 6 d1 ecl, cml, lvcmos, lvds, lvttl input noninverted differential input 1. internal 75 k to v ee . 7 d1 ecl, cml, lvcmos, lvds, lvttl input inverted differential input 1. internal 75 k to v ee and 36.5 k to v cc . 8 vtd1 ? internal 50 termination pin. see table 7. (note 1) 9 v cc ? positive supply voltage (note 2) 10 q rsecl output noninverted differential output. typically terminated with 50 resistor to v tt = v cc ? 2 v. 11 q rsecl output inverted differential output. typically terminated with 50 resistor to v tt = v cc ? 2 v 12 v ee ? negative supply voltage (note 2) 13 vtd0 ? internal 50 termination pin. see table 7. (note 1) 14 d0 ecl, cml, lvcmos, lvds, lvttl input inverted differential input 0. internal 75 k to v ee and 36.5 k to v cc . 15 d0 ecl, cml, lvcmos, lvds, lvttl input noninverted differential input 0. internal 75 k to v ee . 16 vtd0 ? internal 50 termination pin. see table 7. (note 1) ? ep ? the exposed pad (ep) and the qfn?16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat? sinking conduit. the pad is electrically connected to the die but may be electrically and thermally connected to v ee on the pc board. 1. in the differential configuration when the input termination pins (vtdx, vtdx , vtsel) are connected to a common termination voltage, or left open, and if no signal is applied then the device will be susceptible to self?oscillation. 2. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. 3. when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, 2 k resistor should be connected from ols pin to v ee .
nbsg86a http://onsemi.com 3 table 2. output level select ols ols q/q vpp ols sensitivity v cc 800 mv ols ? 75 mv v cc ? 0.4 v 200 mv ols 150 mv v cc ? 0.8 v 600 mv ols 100 mv v cc ? 1.2 v 0 ols 75 mv v ee (note 4) 400 mv ols 100 mv float 600 mv n/a 4. when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, 2.0 k resistor should be connected from ols to v ee . figure 2. logic diagram d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel r 1 r 2 r 1 r 1 r 2 r 1 q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel figure 3. configuration for and/nand function v cc vt or v bb d0 d0 d1 d1 v ee v cc table 3. and/nand truth table (note 5) * d0 d1 sel q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 5. d0 , d1 , sel are inverse of d0, d1, sel unless specified other- wise.
nbsg86a http://onsemi.com 4 figure 4. configuration for or/nor function table 4. or/nor truth table** 0 0 1 1 d0 1 1 1 1 d1 0 1 0 1 sel or 0 1 1 1 q q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel v cc vt or v bb d0 d0 d1 d1 ** d0 , d1 , sel are inverse of d0, d1 , sel unless specified otherwise. q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel d0 d0 d1 d1 figure 5. configuration for xor/xnor function 1 0 0 d1 0 1 0 1 sel xor 0 1 1 0 q table 5. xor/xnor truth table** 0 0 1 1 d0 1 ** d0 , d1 , sel are inverse of d0, d1, sel unless specified oth- erwise. d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel figure 6. configuration for 2:1 mux function d1 d0 q table 6. 2:1 mux truth table** 1 0 sel ** d0 , d1 , sel are inverse of d0, d1, sel unless specified otherwise.
nbsg86a http://onsemi.com 5 table 7. interfacing options interfacing options connections cml connect vtd0, vtd1, vtsel and vtd0 , vtd1 to v cc lvds connect vtd0, vtd1, vtd0 and vtd1 together. leave vtsel open. ac?coupled bias vtd0, vtd1, vtsel and vtd0 , vtd1 inputs within (vihcmr) common mode range rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage should be applied to the unused complementary differential input. nominal voltage 1.5 v for lvttl and v cc /2 for lvcmos inputs. table 8. attributes characteristics value internal input pulldown resistors (r 1 ) 75 k internal input pullup resistor (r 2 ) 37.5 k esd protection human body model machine model charged device model > 1 kv > 50 v > 4 kv moisture sensitivity (note 6) pb?free level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count meets or exceeds jedec spec eia/jesd78 ic latchup test 6. for additional information, see application note and8003/d. table 9. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ?3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ?3.6 v v v inpp differential input voltage |d n ? d n |, |sel ? sel | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) (note 7) 0 lfpm 500 lfpm 41.6 35.2 c/w c/w jc thermal resistance (junction?to?case) 2s2p (note 7) 4.0 c/w t sol wave solder pb?free < 3 sec @ 260 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 7. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nbsg86a http://onsemi.com 6 table 10. dc characteristics, input with lvpecl output v cc = 2.5 v; v ee = 0 v, t a = ?40 c to +85 c (note 8) symbo l characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max power supply current i ee negative power supply current 23 30 39 23 30 39 23 30 39 ma lvpecl outputs (note 9) v oh output high voltage 1460 1510 1560 1490 1540 1590 1515 1565 1615 mv v ol output low voltage (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) (ols = v ee ) 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1385 1015 1585 1215 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1420 1050 1620 1250 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1445 1080 1640 1275 mv v outpp output voltage amplitude (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) (ols = v ee ) 670 125 510 0 325 800 215 615 5 415 660 120 505 0 320 795 210 610 0 410 655 120 500 0 320 790 210 605 5 410 mv differential clock inputs driven single?ended (figures 11 & 13) (note 10) v ih input high voltage (single?ended) d, d , sel, sel 1200 v cc 1200 v cc 1200 v cc mv v il input low voltage (single?ended) d, d , sel, sel 0 v cc ? 150 0 v cc ? 150 0 v cc ? 150 mv v th input threshold reference voltage range (note 11) 950 v cc ?75 950 v cc ?75 950 v cc ?75 mv v ise single?ended input voltage (v ih ? v il ) 150 2600 150 2600 150 260 mv differential inputs driven differentially (figures 12 & 14) (note 12) v ihd differential input high voltage (d, d , sel, sel ) 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage (d, d , sel, sel ) 0 v cc ? 75 0 v cc ? 75 0 v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) (d, d , sel, sel ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (differential configuration) (note 13) (figure 15) 1200 2500 1200 2500 1200 2500 mv i ih input high current (@v ih ) d, d sel, sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel, sel 20 5 100 50 20 5 100 50 20 5 100 50 a termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. input and output parameters vary 1:1 with v cc . 9. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 10. vth, v ih , v il,, and v ise parameters must be complied with simultaneously. 11. vth is applied to the complementary input when operating in single?ended mode. v th = (v ih ? v il ) / 2. 12. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal.
nbsg86a http://onsemi.com 7 table 11. dc characteristics, input with lvpecl output v cc = 3.3 v; v ee = 0 v, t a = ?40 c to +85 c (note 14) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max power supply current i ee negative power supply current 23 30 39 23 30 39 23 30 39 ma lvpecl outputs (note 15) v oh output high voltage 2260 2310 2360 2290 2340 2390 2315 2365 2415 mv v ol output low voltage (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2180 1790 2390 1995 1360 2065 1585 2290 1820 1510 2125 1705 2340 1910 1660 2215 1825 2420 2030 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2240 1855 2445 2060 mv v outpp output amplitude voltage (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) 705 130 535 0 345 815 220 640 0 435 695 125 530 0 340 805 215 635 0 430 690 125 525 0 335 800 215 630 0 425 mv differential clock inputs driven single?ended (figures 11 & 13) (note 16) v ih input high voltage (single?ended) d, d , sel, sel 1200 v cc 1200 v cc 1200 v cc mv v il input low voltage (single?ended) d, d , sel, sel 0 v cc ? 150 0 v cc ? 150 0 v cc ? 150 mv v th input threshold reference voltage range (note 17) 950 v cc ?75 950 v cc ?75 950 v cc ?75 mv v ise single?ended input voltage (v ih ? v il ) 150 2600 150 2600 150 2600 mv differential inputs driven differentially (figures 12 & 14) (note 18) v ihd differential input high voltage (d, d , sel, sel ) 1200 v cc 1200 v cc 1200 v cc mv v ild differential input low voltage (d, d , sel, sel ) 0 v cc ? 75 0 v cc ? 75 0 v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) (d, d , sel, sel ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (differential configuration) (note 19) (figure 19) 1200 3300 1200 3300 1200 3300 mv i ih input high current (@v ih ) d, d sel, sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel, sel 20 5 100 50 20 5 100 50 20 5 100 50 a termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . 14. input and output parameters vary 1:1 with v cc . 15. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 16. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 17. v th is applied to the complementary input when operating in single?ended mode. v th = (v ih ? v il ) / 2. 18. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 19. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal.
nbsg86a http://onsemi.com 8 table 12. dc characteristics, necl input with necl output v cc = 0 v; v ee = ?3.465 v to ?2.375 v, t a = ?40 c to +85 c (note 20) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max power supply current i ee negative power supply current 23 30 39 23 30 39 23 30 39 ma lvpecl outputs (note 21) v oh output high voltage ?1040 ?990 ?940 ?1010 ?960 ?910 ?985 ?935 ?885 mv v ol output low voltage ?3.465 v v ee ?3.0 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) **(ols = v ee ) ?3.0 v < v ee ?2.375 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) (ols = v ee ) ?1980 ?1270 ?1750 ?1040 ?1515 ?1945 ?1265 ?1725 ?1045 ?1495 ?1830 ?1210 ?1630 ?990 ?1425 ?1795 ?1205 ?1605 ?995 ?1405 ?1680 ?1120 ?1510 ?910 ?1305 ?1645 ?1115 ?1485 ?915 ?1285 ?1940 ?1235 ?1715 ?1010 ?1480 ?1905 ?1230 ?1690 ?1010 ?1460 ?1790 ?1175 ?1595 ?960 ?1390 ?1755 ?1170 ?1570 ?960 ?1370 ?1640 ?1085 ?1475 ?880 ?1270 ?1605 ?1080 ?1450 ?880 ?1250 ?1910 ?1210 ?1685 ?985 ?1450 ?1875 ?1205 ?1660 ?990 ?1435 ?1760 ?1150 ?1565 ?935 ?1360 ?1725 ?1145 ?1540 ?940 ?1345 ?1610 ?1060 ?1445 ?855 ?1240 ?1575 ?1055 ?1420 ?860 ?1225 mv v outpp output voltage amplitude ?3.465 v v ee ?3.0 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) ?3.0 v < v ee ?2.375 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) (ols = v ee ) 705 130 535 0 345 670 125 510 0 325 815 220 640 0 435 800 215 615 5 415 695 125 530 0 340 660 120 505 0 320 805 215 635 0 430 795 210 610 0 410 690 125 525 0 335 655 120 500 0 320 800 215 630 0 425 790 210 605 5 410 mv differential clock inputs driven single?ended (figures 11 & 13) (note 22) v ih input high voltage (single?ended) d, d , sel, sel v ee + 1200 v cc v ee + 1200 v cc v ee + 1200 v cc mv v il input low voltage (single?ended) d, d , sel, sel v ee v ih ? 150 v ee v ih ? 150 v ee v ih ? 150 mv v th input threshold reference voltage range (note 23) v ee + 950 v cc ?75 v ee + 950 v cc ?75 v ee + 950 v cc ?75 mv v ise single?ended input voltage (v ih ? v il ) 150 2600 150 2600 150 2600 mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . 20. input and output parameters vary 1:1 with v cc . 21. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 22. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 23. v th is applied to the complementary input when operating in single?ended mode. v th = (v ih ? v il ) / 2. 24. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 25. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal.
nbsg86a http://onsemi.com 9 table 12. dc characteristics, necl input with necl output v cc = 0 v; v ee = ?3.465 v to ?2.375 v, t a = ?40 c to +85 c (note 20) symbol unit 85 c 25 c ?40 c characteristic symbol unit max typ min max typ min max typ min characteristic differential inputs driven differentially (figures 12 & 14) (note 24) v ihd differential input high voltage (d, d , sel, sel ) v ee + 1200 v cc v ee + 1200 v cc v ee + 1200 v cc mv v ild differential input low voltage (d, d , sel, sel ) v ee v cc ? 75 v ee v cc ? 75 v ee v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) (d, d , sel, sel ) 75 2600 75 2600 75 2600 mv v ihcmr input high voltage common mode range (differential configuration) (note 25) (figure 15) v ee + 1200 0 v ee + 1200 0 v ee + 1200 0 mv i ih input high current (@v ih ) d, d sel, sel 30 5 100 50 30 5 100 50 30 5 100 50 a i il input low current (@v il ) d, d sel, sel 20 5 100 50 20 5 100 50 20 5 100 50 a termination resistors r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . 20. input and output parameters vary 1:1 with v cc . 21. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 22. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 23. v th is applied to the complementary input when operating in single?ended mode. v th = (v ih ? v il ) / 2. 24. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 25. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren- tial input signal.
nbsg86a http://onsemi.com 10 table 13. ac characteristics v cc = 0 v; v ee = ?3.465 v to ?2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum input clock frequency (see figure 7) (note 26) 7 8 7 8 7 8 ghz v outpp output voltage amplitude f in 7 ghz (ols = v cc )f in = 8 ghz 590 270 730 440 470 230 720 420 540 180 700 390 mv mv t plh , t phl propagation delay to output differential (figure 16) d/sel q 110 160 210 115 165 215 120 170 220 ps t skew duty cycle skew (note 27) 5 15 5 15 5 15 ps t skew channel skew q d/sel 5 20 5 20 5 20 ps t s set?up time (dx to sel) 30 30 30 ps t h hold?up time (dx to sel) 35 35 35 ps t jitter rms random clock jitter (see figure 7) (note 29) f in 7 ghz peak?to?peak data dependent jitter (note 30) f in 7 gb/s 0.5 12 1.5 0.5 12 1.5 0.5 12 1.5 ps v inpp input voltage swing/sensitivity (differential configuration) (note 28) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% ? 80%) (q, q ) t r @ 1 ghz t f 30 17 45 35 60 65 30 17 45 35 60 65 30 17 45 35 60 65 ps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 26. measured using a 500 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 27. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. see figure 16. 28. v inpp (max) cannot exceed v cc ? v ee . 29. additive rms jitter with 50% duty cycle clock signal at 7 ghz. 30. additive peak?to?peak data dependent jitter with nrz prbs 2 31 ?1 data rate at 7 gb/s.
nbsg86a http://onsemi.com 11 rms jitter input frequency (ghz) output voltage amplitude (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 12345678910 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc ? 0.4 v *ols = v ee ols = v cc ? 0.8 v ols = float rms jitter input frequency (ghz) output voltage amplitude (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 12345678910 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc ? 0.4 v *ols = v ee ols = v cc ? 0.8 v, ols = float figure 7. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for 2:1 mux mode (v cc ? v ee = 2.5 v @ 25 c; repetitive 1010 input data pattern) figure 8. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for 2:1 mux mode (v cc ? v ee = 3.3 v @ 25 c; repetitive 1010 input data pattern) *when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg86a http://onsemi.com 12 i ols ( a) ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 300 figure 9. typical ols input current vs. ols input voltage (v cc ? v ee = 3.3 v @ 25 c) v ols (mv) v outpp (mv) 0 200 400 600 800 1000 ols (mv) figure 10. ols operating area v ee v cc v cc ? 400 v cc ? 800 v cc ? 1200 v ee v cc v cc ? 400 v cc ? 800 v cc ? 1200 v cc ? 75 v cc ? 250 v cc ? 550 v cc ? 700 v cc ? 900 v cc ? 1125 v cc ? 1275 v ee + 100
nbsg86a http://onsemi.com 13 in v th in v th figure 11. differential input driven single?ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin v ee v th in in v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v ihcmr v ee v id = v ihd ? v ild v cc v ihd v ild v id = |v ihd(in) ? v ild(in )| in in figure 12. differential inputs driven differentially figure 13. v th diagram figure 14. differential inputs driven differentially figure 15. v ihcmr diagram figure 16. ac reference measurement in in v ihcmrmax v ihcmrmin in d d q q t phl t plh v inpp (d) = v ih (d) ? v il (d) v outpp (q) = v oh (q) ? v ol (q) v inpp (d ) = v ih (d ) ? v il (d ) v outpp (q ) = v oh (q ) ? v ol (q ) figure 17. selx to qx timing diagram sel qx t phl t plh qx
nbsg86a http://onsemi.com 14 application information all nbsg86a inputs can accept pecl, cml, lvttl, l vcmos and lvds signal levels. the limitations for differential input signal (lvds, pecl, or cml) are minimum input swing of 75 mv and the maximum input swing of 2500 mv . within these conditions, the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). for output termination and interface, refer to application note and8020/d. table 14. interfacing options interfacing options connections cml connect vtd and vtd to v cc (see figure 18) lvds connect vtd and vtd together (see figure 20) ac?coupled bias vtd and vtd inputs within common mode range (v cmr ) (see figure 19) rsecl, pecl, necl standard ecl termination techniques (see figure 22) lvttl, lvcmos an external voltage (v thr ) should be applied to the unused complementary differential input. nominal v thr is 1.5 v for lvttl and v cc / 2 for lvcmos inputs. this voltage must be within the v thr specification. (see figure 21) 50 v cc d d 50 nbsg86a v cc vtd v ee v cc q 50 50 cml driver v ee figure 18. cml interface q z = 50 figure 19. pecl interface 50 v cc v cc pecl driver d d 50 nbsg86a v ee v bias * vtd v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values vtd v cc vtd v bias * z = 50 z = 50 z = 50 c c *v bias must be within common mode range limits (v cmr )
nbsg86a http://onsemi.com 15 50 v cc v cc lvds driver d d 50 nbsg86a v ee vtd v ee vtd figure 20. lvds interface figure 21. lvcmos/lvttl interface 50 v cc v cc lvttl/ lvcmos driver d d 50 nbsg86a v ee vtd v cc v ref lvcmos v cc ? v ee 2 lvttl 1.5 v recommended v ref values vtd v ref no connect* no connect *or 60 pf to gnd z = 50 z = 50 z = 50 figure 22. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v
nbsg86a http://onsemi.com 16 ordering information device package type shipping ? nbsg86amng qfn16 (pb?free / halide?free) 123 units / rail nbsg86amnr2g qfn16 (pb?free / halide?free) 3000 / tape & reel NBSG86AMNHTBG qfn16 (pb?free / halide?free) 100 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging spe- cifications brochure, brd8011/d.
nbsg86a http://onsemi.com 17 package dimensions ??? ??? ??? case 485g issue f 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters . 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nbsg86a/d gigacomm is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

▲Up To Search▲

Price & Availability of NBSG86AMNHTBG

	To Download NBSG86AMNHTBG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .